In general layout design of semiconductor integrated circuits, after the positions of macro cells to be placed are determined, power supply wirings are automatically arranged at certain intervals in each wiring layer. In a row region or macro cell where lack of power supply wiring occurs, a power supply wiring is manually inserted and connected.
To prevent insertion error or misconnection of power supply wirings, which is caused by the manual operation, for example, Japanese Laid-open Patent Publication No. 10-199987 discloses a technique in which connectivity is checked after the formation of power supply wirings. In the technique, a power supply network analysis for simulating the current density and the amount of voltage drop is further made to search for a portion including a power supply wiring to be corrected and the wiring is corrected accordingly.
However, the technique of the related art described above in which a power supply wiring is manually inserted and connected has a problem in that designing a manual layout of power supply wirings is time-consuming.
Other problems also arise. In the process of checking connectivity after the completion of power supply wiring, it is difficult to detect a portion including voltage drop although it is possible to detect a portion where no wiring is formed. In a power supply network analysis for detecting a power drop, the extraction of resistance values and capacitance values of the power supply wirings and the calculation of power consumption require much time. Every correction of power supply wiring requires to retry the layout design, and the load on the design engineer as well as the period of layout design may be increased.